if a cache controller invalidates the line its cache when it sees a request for modified access to a line, and then that requesting cache ends up overwriting that line before the original controller receives a request for that line, would the cache-miss latency be larger, since it has to go to the owning cache and then main memory?

Is there ever a case where the overhead of communication to send all other caches messages when a processor writes is large such that the program would be better off without using caches? (i.e. a program that have lots of writes to memory?)

@xiyan if the different processors are accessing (reading, writing) different regions of memory, then the cache coherence protocol isn't necessary because we know the caches of the processors will have nothing in common. In this case, there would be overhead of sending BusRead and BusReadX over the bus while the other processors don't need to do anything to that information. So in some applications this overhead does exist and doesn't help.

Although in practice (correct me if I am wrong), programs can't choose to use the cache or not; that's implemented by the hardware memory system.