Single - Writer, Multiple- Read Invariant is maintained with the notion of a cache being the exclusive owner of a block of memory and the busRdX action that signals to the rest of the processors that the cache requests to be the sole owner of this line
The write serialization is ensured by the bus. The bus serializes all transactions.
Summary related to the 2 questions above.
Single - Writer, Multiple- Read Invariant is maintained with the notion of a cache being the exclusive owner of a block of memory and the busRdX action that signals to the rest of the processors that the cache requests to be the sole owner of this line
The write serialization is ensured by the bus. The bus serializes all transactions.