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When we refer to sequential consistency with respect to many processors, do we mean that each processors issue their respective loads and stores in program order?


@martigp looking at the other examples from this lecture, yes, I think that's right. Imagine if you had

Proc 0: Instr A Instr B

Proc 1: Instr C Instr D

Sequential consistency across these multiple processors would make ABCD, ACBD, CDAB, and CABD valid memory operation orders, but for example BACD or ADBC would be invalid. The switch metaphor of thinking about only one operation for the whole system happening at once makes this easier to digest.

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