Is it fair to say that when we talk about re-ordering memory operations, we don't re-order when the memory operation is issued, but rather we no longer restrict ourselves to wait for a previous one to complete before issuing another one? This would mean the operation issued second can complete before the operation issued first as was explained with the two writes where one is a cache hit and one is a cache miss.
I understand that this makes sense, but I'm wondering if relaxing the write_x -> write_y constraint means that a thread might issue the write_y operation before the write_x operation despite write_x appearing before write_y in program order.
If A is a cache miss while flag is a hit, then we risk thread 2 observing the change to flag and then printing before A is updated. This is because the Wx -> Wy memory operation ordering can be violated, meaning that the second write doesn't necessarily finish before the first write.
Are there no orderings where you relax just the w_x -> w_y? What would be the problem there?
Please log in to leave a comment.