If we have multiple DIMMs per channel (e.g. many motherboards have 2 channels for RAM but 4 DIMM slots), then do the two DIMMs share the same 64 bit bus or do we have access to 128 bit bus now? I assume the former but doesn't this mean now that we have effectively half the bandwidth per DIMM since there must be some scheduling as to which DIMM is outputting data to the bus? If so is that handled by a memory controller?

@parthiv, I believe we actually do double the bus size.