These diagrams of real-world chips really help put into perspective the complexity of parallel programming. It is amazing to think about the insane number of constraints and considerations that go into building chips such as Apple's A11 Bionic which has to be manufactured and distributed to millions of users.

I'm curious what's up with the placement of cpu and gpu cores on the chip, e.g. the little and big cpu cores are spaced pretty far apart and the GPU cores have a somewhat irregular placement. I wonder why they chose to design the chip this way...

As a non-EE person who has close to zero understanding of hardware, I'm curious what I should take away from these diagrams. Do others have a "main takeaway" from looking at these examples?

@tcr, I think the main takeaway would be that modern systems are heterogenous with different sized cores and bunch and a bunch of accelerators to achieve higher efficiency (and performance).

In lecture, we discussed how many functions we now perform (and take for granted on mobile phones) that necessitate the need for heterogenous processors: ex. taking nice photos and videos, and rendering fancy games with high frame rates.

It was really interesting in the chat, Kayvon mentioned some of the complications that make picture and videos the most computationally intensive task for phones. Phones will apparently perform a significant amount of work to create the best phone, including compositing multiple images using AI and autofocus.

@lindenli The (main) reason why mobile phones are so heterogeneous is because of power usage. While it is nice to be able to decode video streams faster, using dedicated HW for video decode saves significant power, letting you use your phone for longer.

@terribilis I think that because phones are inherently limited in size, there is only so much you can do with limited lens/sensor sizes so processing images becomes important. Nowadays it seems like the camera is a large selling point of new phones, so it makes sense to add all this processing.

It seems that DDR (memory) is located on the edges of the Apple A11 chip: are there energy-cooling or other considerations in deciding the location of different components? It would seem that being on the edge of a chip allows for more cooling.