THIS REVIEW WAS SO HELPFUL!!!

Here's how I'm understanding an example use case:
- OS gives this chip 8 threads to run; these are represented in the 4 execution contexts - At any one clock, the scheduling system on each core will choose at most one scalar instruction and one vector instruction to run from its available instruction streams. These instructions could be from the same or different instruction streams, but they must be independent.

I don't see the point of having more execution contexts than ALU units since at most we can only run 2 instructions (1 vector and 1 scalar) at once. Is it to increase the chance of parallelization by having more instruction streams to choose from?