These diagrams are helpful. As the F/D and Exec Context are what really helps understand how much parallelism happens. Without these pictures, concepts would be confusing. So nice to have these.

The classic model of the CPU is a five-stage RISC/MIPS CPU (although nowadays more stages are involved to help with throughput and allow for higher clock speed, though there are diminishing returns on adding stages).

The first two stages are instruction fetching/decoding. The next stage is execute. The two final stages are memory and register write back (whether reading/writing from cache or memory). Stalls are necessarily added when reading from memory (unless other work can be done in the interim, and the CPU orders out-of-order execution) because it is slower than cache.