Stanford CS149, Fall 2021
PARALLEL COMPUTING
From smart phones, to multi-core CPUs and GPUs, to the world's largest supercomputers and web sites, parallel processing is ubiquitous in modern computing. The goal of this course is to provide a deep understanding of the fundamental principles and engineering trade-offs involved in designing modern parallel computing systems as well as to teach parallel programming techniques necessary to effectively utilize these machines. Because writing good parallel programs requires an understanding of key machine performance characteristics, this course will cover both parallel hardware and software design.
Basic Info
Tues/Thurs 3:15-4:45pm
All lectures are virtual
Instructors: Kayvon Fatahalian and Kunle Olukotun
See the course info page for more info on policies and logistics.
Fall 2021 Schedule
| Sep 21 |
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Challenges of parallelizing code, motivations for parallel chips, processor basics
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| Sep 23 |
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Forms of parallelism: multicore, SIMD, threading + understanding latency and bandwidth
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| Sep 28 |
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Ways of thinking about parallel programs, and their corresponding hardware implementations, ISPC programming
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| Sep 30 |
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Thought process of parallelizing a program in data parallel and shared address space models
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| Oct 05 |
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Achieving good work distribution while minimizing overhead, scheduling Cilk programs with work stealing
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| Oct 07 |
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Message passing, async vs. blocking sends/receives, pipelining, increasing arithmetic intensity, avoiding contention
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| Oct 12 |
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CUDA programming abstractions, and how they are implemented on modern GPUs
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| Oct 14 |
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Data-parallel operations like map, reduce, scan, prefix sum, groupByKey
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| Oct 19 |
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Producer-consumer locality, RDD abstraction, Spark implementation and scheduling
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| Oct 21 |
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Definition of memory coherence, invalidation-based coherence using MSI and MESI, false sharing
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| Oct 26 |
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Consistency vs. coherence, relaxed consistency models and their motivation, acquire/release semantics
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| Oct 28 |
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Implementation of locks, fine-grained synchronization via locks, basics of lock-free programming: single-reader/writer queues, lock-free stacks, the ABA problem, hazard pointers
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| Nov 02 |
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No class (Stanford Election Day Holiday)
Go vote!
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| Nov 04 |
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Motivation for transactions, design space of transactional memory implementations.
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| Nov 09 |
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Finishing up transactional memory focusing on implementations of STM and HTM.
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| Nov 11 |
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Energy-efficient computing, motivation for heterogeneous processing, fixed-function processing, FPGAs, mobile SoCs
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| Nov 16 |
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Performance/productivity motivations for DSLs, case study on Halide image processing DSL
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| Nov 18 |
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domain-specific frameworks for graph processing, streaming graph processing, graph compression, DRAM basics
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| Nov 30 |
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Programming reconfigurable hardware like FPGAs and CGRAs
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| Dec 02 |
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Scheduling conv layers, exploiting precision and sparsity, DNN acelerators (e.g., GPU TensorCores, TPU)
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Programming Assignments
Written Assignments
| Sep 30 | Written Assignment 1 |
| Oct 7 | Written Assignment 2 |
| Oct 26 | Written Assignment 3 |
| Nov 10 | Written Assignment 4 |
| Nov 30 | Written Assignment 5 |