I didn't quite understand where this MSI protocol is being implemented. It sounds like not the OS because we wanted to avoid slowness. Is this protocol implemented closer to the hardware? How exactly does all this message sending and receiving infrastructure work? I see that the processor operations are "triggered by local CPU", but where is the actual code for this written if not in the OS?

This protocol is implemented strictly in hardware. It is not implemented through code. As discussed in other slides, this is implemented via interconnect networks like the bus to facilitate communication between cache controllers of all private caches in the computer.

I don't quite understand how this is implemented strictly in hardware. Where do the cache controllers keep track of which state (I, S, or M) each cache is in?

Summary of the MSI protocol: 3 cache line states(M, S, I). 2 Ops by CPU(Rd, Wr). 3 Bus transactions (Rd, RdX, WB)