each process keeps track of its own state. whenever a process initiate a write or read, a bus read or bus read exclusive is triggered and could in turn trigger bus write back.

I'm a little confused on the processor initiated vs bus initiated distinction. If the processor writes lines in the modified state, isn't the bus also initiated to set the other states to inactive?

Can someone please explain how the Bus initiated state transitions occur? I understand when we talk about the green processor initiated transitions go but I think the right side of the diagram when we are transitioning back from M to S to I is not as intuitive to think about. Are bus transitions essentially initiated by another cache / processor, and this MSI diagram is only valid for one cache / processor at a time, hence the Pr transitions?

+1 on Mark's question. I don't really understand how is each request/action performed and is it serialized with one another or can we run them concurrently?