Does the existence of multiple protocols means that a program that has been optimized for performance on one CPU that uses one coherence protocol may not perform as well on another processor that uses another coherence protocol?
Suppose you are a sequential program, which is one that doesn’t share state. This means that, in order to read a cache line and write to it, you have to do 2 steps. First, you have to move from the invalid state to the shared state. Then, you have to move into the M state. This is highly inefficient. How do we address this issue? Suppose we add an additional state, which we call an “exclusive clean” state. Exclusive clean means you’re the only processor with the cache line - no other processor is sharing it. If you issue a bus read for a cache line and no one else is responding, then you can move cache line from the invalid state to the exclusive clean state.
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