As we saw in instruction pipelining earlier in the quarter, in the pipelined schedule above, the steady state effective initiation interval in a full pipeline is the length of the longest stage.

What like does the fifoOut and fifoIn play in this instance, is this the data structure that has to be used by the Stream Schedule, if so why is that the case over sram?

In Pipelined schedule, you have different stages for different computations. Longer the pipeline, greater the parallelism. As noted, "Closest thing to free lunch in hardware." -John Hennessey