Is this always a consistent number of clock cycles, or is there any uncertainty associated with memory access latency? It seems like transferring a bit from DRAM to the CPU could be subject to physical interference (e.g., a cosmic ray flips the bit in transit).

A memory access can definitely take a variable number of clock cycles. There are many reasons why: the state of the system (depth of various queues), contention for communication channels, what address in memory is accessed, what addresses have recently been accessed. etc etc. We'll talk a bit more about how memory works in later lectures.