More information on HTM, from Kayvon's comments in lecture: HTM is a fully hardware-based implementation of the same semantics discussed in STM, to reduce overhead. This is done with a small tweak to a write-back cache that already implements its own coherence protocol. This is because a cache already has a way to track "dirty" lines, so now we just need a way to track which lines were read (and written) during the current transaction! That's just an additional two bits per line.
More information on HTM, from Kayvon's comments in lecture: HTM is a fully hardware-based implementation of the same semantics discussed in STM, to reduce overhead. This is done with a small tweak to a write-back cache that already implements its own coherence protocol. This is because a cache already has a way to track "dirty" lines, so now we just need a way to track which lines were read (and written) during the current transaction! That's just an additional two bits per line.