From smart phones, to multi-core CPUs and GPUs, to the world's largest supercomputers and web sites, parallel processing is ubiquitous in modern computing. The goal of this course is to provide a deep understanding of the fundamental principles and engineering trade-offs involved in designing modern parallel computing systems as well as to teach parallel programming techniques necessary to effectively utilize these machines. Because writing good parallel programs requires an understanding of key machine performance characteristics, this course will cover both parallel hardware and software design.
Why Parallelism? Why Efficiency?
Challenges of parallelizing code, motivations for parallel chips, processor basics
A Modern Multi-Core Processor
Multi-Core Arch II + ISPC Programming Abstractions
Multi-Core Architecture Part II + ISPC Programming Abstractions
Finish up multi-threaded and latency vs. bandwidth. ISPC programming, abstraction vs. implementation
Parallel Programming Basics
Ways of thinking about parallel programs, thought process of parallelizing a program in data parallel and shared address space models
Performance Optimization I: Work Distribution and Scheduling
Achieving good work distribution while minimizing overhead, scheduling Cilk programs with work stealing
Performance Optimization II: Locality, Communication, and Contention
Message passing, async vs. blocking sends/receives, pipelining, increasing arithmetic intensity, avoiding contention
GPU architecture and CUDA Programming
CUDA programming abstractions, and how they are implemented on modern GPUs
Data-parallel operations like map, reduce, scan, prefix sum, groupByKey
Distributed Data-Parallel Computing Using Spark
Producer-consumer locality, RDD abstraction, Spark implementation and scheduling
Efficiently Evaluating DNNs on GPUs
Efficiently scheduling DNN layers, mapping convs to matrix-multiplication, transformers, layer fusion
Definition of memory coherence, invalidation-based coherence using MSI and MESI, false sharing
Implementing Locks + A Bit on Memory Consistency
implementation of locks, relaxed consistency models and their motivation, acquire/release semantics
Democracy Day (no class)
Take time to volunteer/educate yourself/take action!
Fine-Grained Synchronization and Lock-Free Programming
Fine-grained synchronization via locks, basics of lock-free programming: single-reader/writer queues, lock-free stacks, the ABA problem, hazard pointers
Midterm Exam (no class)
The midterm will be an evening midterm. We may use the class period as a review period.
Domain Specific Programming Languages
Performance/productivity motivations for DSLs, case studies on several DSLs
Transactional Memory 1
Motivation for transactions, design space of transactional memory implementations.
Transactional Memory 2
Finishing up transactional memory focusing on implementations of STM and HTM.
Energy-efficient computing, motivation for heterogeneous processing, fixed-function processing, FPGAs, mobile SoCs
Programming for Hardware Specialization
Programming reconfigurable hardware like FPGAs and CGRAs
Held at 3:30pm. Location TBD
|Oct 6||Assignment 1: Analyzing Parallel Program Performance on a Quad-Core CPU|
|Oct 19||Assignment 2: Scheduling Task Graphs on a Multi-Core CPU|
|Nov 28||Assignment 4: Chat149 - A Flash Attention Transformer DNN|
|Dec 8||[Optional Assignment 5]: Big Graph Processing|
|Oct 10||Written Assignment 1|
|Oct 23||Written Assignment 2|
|Oct 30||Written Assignment 3|
|Nov 10||Written Assignment 4|
|Dec 6||Written Assignment 5|