What are the control templates used for? Is there an analogous version or some metaphor to help with understanding this?

I'm confused about the blocking/non-blocking interaction with CPU. I thought Spatial will compile to Verilog (or other hardware language). Why the control templates interact with CPU?

The template also looks like an always block with sensitivity list in Verilog. Is the Accel block here related to that?

@gomi On a previous page, someone mentioned that Spatial compiles into Chisel which compiles into Verilog, so it may be very likely that there's a strong connection between the Accel block and Verilog.